• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to telecommunication can be used for full duplex digital signals. The purpose of the invention is the provision of signal transmission over a two-wire communication line. The system contains the main terminal, consisting of generators (HS) I, block 2 synchronization, transceiver 3, block 4 prohibition of the transmitted signal (BZPS) and discriminator 5, as well as a peripheral terminal consisting of transceiver 6, BZPS 7, discriminator 8, unit 9 of the selection of the sync pulse (EVSI), block 10 synchronization and HS 11. In the main terminal, the digital output signal HS 1 is converted to transceiver-1ik 3 into a pulse with a return to zero, having a narrow width, which is sprinkled on the transmission line. At the same time, the transceiver 3 transmits a signal that is sent from the peripheral terminal to the BZPS 4. The CCTV 4 prevents the digital signal that comes from the HS 1 to the discriminator 5. In the peripheral terminal, transceiver 6 transmits a pulse to discriminator 8 via RFPP 7. At the same time, a pulse is sent from BWPS 7 to BVSI 9. The selected synchronization pulse is sent to the synchronization unit 10, which generates a pulse to send a digital signal from the GPS 11 and a pulse to the RFID 7. Thus, the next signal from the perimeter CM
    公开号:SU1258340A3
    申请号:SU2084150
    申请日:1974-11-11
    公开日:1986-09-15
    发明作者:Мория Такао；Мурано Казуо；Фудзикава Сюнидзи
    申请人:Фудзицу Лимитед (Фирма)；
    IPC主号:
    专利说明:

    The emergency signal is controlled by a synchronization signal, which is derived from the signal sent from the terminal. The goal reaches 1
    The invention relates to telecommunications and can be used for the duplex transmission of digital signals.
    The aim of the invention is to provide signaling over a two-wire communication line.
    Fig. 1 shows a structured electrical circuit of the proposed system; in D.2 - an embodiment of the main and peripheral terminals; figure 3 - timing diagrams.
    The duplex time-division signaling system comprises in the main terminal a signal generator 1, a synchronization unit 2, a transceiver 3, a transmission prohibition block 4, a discriminator 5, and a transceiver 6 in the peripheral terminal, a transmission prohibition block 7, a discriminator 8, a block 9 sync highlighting. pulse block 10 synchronization and generator P signals.
    An implementation option of the main terminal contains a trigger 12, a multivibrator 13, the first element And 14, the first transistor 15, the second element And 16, the second transistor 17, the transformer 18, the element And 19, the inverter 20.
    A variant of the implementation of the peripheral thermgol contains a transformer 21, the first element And 22, the second element And 23, the trigger 24, the transistor 25, the element OR 26, the delay line 27, the third element And 28, the inverter 29.
    The system works as follows.
    In the main terminal, the 1-signal generator amplifies a non-returning zero digital information signal with a constant bit rate. The synchronization of this constant bit rate is determined by the clock signal from synchronization unit 2. Digital output
    with the introduction of the BISS and 7, the discriminator 5, the ACI 9 and the HS 11. The options for the implementation of the main and peripheral terminals are given. 3 il.
    the signal generator 1 signal is applied to the transceiver 3, which converts the specified digital output signal into a pulse with a return
    5 to zero, which has a narrow width, and sends this pulse to the transmission line. At the same time, transceiver 3 transmits a signal that is sent from the peripheral terminal to block 4 of the transmitted signal prohibition. The block 4 of the prohibition of the transmitted signal prevents the passage of a digital signal that comes from the generator 1 of signals in
     discriminator 5. Block 4 prohibition of the transmitted signal operates in accordance with the clock signals of block 2 synchronization. In the peripheral terminal, the transceiver 6 transmits the received pulse to the discriminator 8 through the prohibition block 7 of the transmitted signal. At the same time, the output pulse from the prohibition block 7 sprinkles onto the clock extract pulse block 9. The selected clock pulse is sent to the synchronization unit 10, which generates a pulse from the specified selected clock pulse to send a digital signal from the signal generator 1 1 and a pulse to the transmitted signal inhibitor block 7, i.e. in the peripheral terminal, the clock pulses are formed from
    35 clock signal sent from the main terminal.
    20
    25
    thirty
    In the proposed device, the sending of a signal from a peripheral terminal is controlled by a synchronization signal, which is extracted from the signal sent from the main terminal, and this creates a complete time-division duplicate system based on digital technology using a digital signal.
    3
    The implementation variant of the main and peripheral terminals works in the following way.
    The digital information (FIG. Zo) signal is supplied by the signal generator 1 in the main terminal to one input of the element 14, and the clock signal (FIG. 3b) is sent from the synchronization unit 2 to the other input of the element 14. signal generator 1 is signal 1. When the signal at the same input of the element AND 14 is 1, the element AND 14 is excited, the current passes through the transistor 15 and has a high level of 1, and when the input signal at one input of the element 14 is equal to O, the element 16 is energized and the current passes through the transistor 17 when the input clock signal is applied (Fig. 38). The outputs of the transistor 15 and transistor 1 7 are connected to the two ends of the winding W1 of the transformer 18, and a voltage source is connected to the middle tap of the winding WI. Consequently, the signal shown in ((1ig.38) appears on the winding W2 of the transformer 18 and is sent to the transmission line. When the input signal at one input of the And 14 1 element appears, pulse P1 appears when the input signal at one input of the element And 14 0 a pulse P2 appears, having a polarity opposite to the pulse Pt, i.e. the signal shown in Fig. 3b is bipolar. Thus, the signal that is sent from the main terminal to the transmission line is always contains synchronization data and the peripheral terminal can extract synchronization from it ruyuschy pulse, using a simple circuit.
    The pulse signal is sent from the main terminal and also appears on the winding W3 of the transformer 18. However, the pulse signal on the winding W3 does not reach the discriminator 5, since element 19 is controlled by a clock signal through the inverter 20. the transmission line is delayed by time before it reaches the peripheral terminal (Fig. 3,), with pulses P1 and P2 with a time delay t relative to pulses P1 and P2 appearing on the winding 5883404
    ke W6 transformer 21 peripheral terminal. Since the middle tap of the winding W4 of the transformer 21 is grounded, the signal shown in Fig. 3g, 5 and the signal of opposite polarity (Fig. 3g) appear respectively at each end of the winding W4 of the transformer 21. Signals that occur at both ends of the winding W4 forbidden
    10, the synchronization from the control clock pulse, which is shown in Fig. 3g, and the signals shown in Fig. 33 and Ze, appear at the outputs of the And 22 and 23 elements, respectively.
    15 These signals are then fed to the set and reset inputs of the trigger 24. Therefore, the input digital signal shown in FIG. 3. appears at the output of trigger 24,
    20 i.e. the output from generator 1 of the signals of the main terminal is allocated by the peripheral terminal.
    The outputs of the And 22 and 23 elements are fed to the OR 26 and
     the synchronization signal shown in FIG. 3) (4 appears at the output of the OR element 26. The main terminal sends a bipolar signal, so the peripheral terminal can easily select the synchronization signal. The synchronization signal (FIG. 3) is sent to the AND element 2. Through the delay line 27. The output signal of the delay line 27 is shown in FIG. 3. Cog5 Yes there is an input signal (Fig. 3J), which is sent from the peripheral terminal to the main terminal, the synchronization of its transmission to the output is controlled by the output clock signal (FIG. Zo)
    0 which is given an extra 27 delay per element AND 28. The scattered signal from the peripheral terminal to the main one is a unipolar signal when the input signal being sent
    5 (FIG. 3) on one And 28 1 element, And 28 is excited and current passes through the transistor 25 at the same time as the clock signal shown in FIG. Zi, of the high G-th level 0 n, while the pulse P10 shown in the (FIG. 3) high level 1., the pulse P10 shown in (FIG. 3g) is sent through the winding W5 of the transformer 21 to the transmission line. Thus, the time delay of the delay line 27 must be greater than the width of the pulse sent from the main terminal.
    The signal from the output of the line 27 is also delayed to the inverter 29. The signal from the output of the inverter 29 (Fig. 3k) is applied to prohibit the operation of elements 22 and 23. Therefore, elements 22 and 23 and 28 are closed and the sprinkled signal 10, which is fed to winding 5 transformer 21 from the peripheral terminal, does not pass through the wrapping W4, elements And 22 and 23 and the trigger 24.
    The signal P10 appears after a time delay on the winding W 3 of the main thermal transformer 18 as well as the signal P10 shown in Fig. 36. The discriminator 5 of the main terminal consists of the element And 19, the multivibrator 13 and the trigger 12. The element And 19 opens with a signal from the output of the inverter 20 (Fig. 3m). When a received signal appears (i.e., pulse P10 shown in FIG. 3b is received from a peripheral terminal), the signal from the output of element I 19 (FIG. 3M) is converted by a single-stable multivibrator 13 into a single-field signal. having a duty cycle of approximately 1. The output signal from the (one-stable) multivibrator 13 is fed to trigger 12, where the clock pulse shown in Fig. 3 is also fed, and the signal at the output of trigger 12, i.e. the selected input digital signal shown in g. the output of the trigger 12 of the main terminal appears.
    The clock signal of the peripheral terminal is extracted from the received signal that is sent from the main terminal, and the sending of the signal from the peripheral terminal is controlled by the clock signal of the peripheral terminal. Therefore, in the main and peripheral terminals, respectively, the signals sent and received correspond to the work of the discriminato)
    1258340
    Ditch 5 and 8 are not at the same time, which allows for two-way full duplex communication in the transmission of each bit of information alternately between the main and peripheral terminals.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    10 Duplex communication system with time division of signals, containing the main terminal, consisting of serially connected synchronization unit, signal generator
    15 and a transceiver that is connected to the communication line, and a peripheral terminal consisting of a transceiver connected to the communication line, a synchronization unit and a discriminator, wherein, in order to transmit signals over the two-wire line, the main terminal entered serially connected block ban
    25 of the transmitted signal and the discriminator, to the clock input of which the second output of the synchronization unit is connected, the third output of which is connected to the clock input of the inhibiting unit
    30 of the transmitted signal, to the information input of which the output of the transceiver is connected, and the signal generator and the series-connected unit are input to the peripheral terminal
    35 of the prohibition of the transmitted signal and the block of the selection of the synchronizing pulse, the output of which is connected to the input of the synchronization unit, the outputs of which are connected respectively to the clock input of the block of the transmission of the transmitted signal, the output of which is connected to the input of the discriminator, and to the input of the signal generator whose output is connected to input transceiver 45 of the sensor, the output of which is connected to the information input of the block prohibiting the transmitted signal.
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    同族专利:
    公开号 | 公开日
    SE407887B|1979-04-23|
    NL164443B|1980-07-15|
    CA1027252A|1978-02-28|
    NL164443C|1980-12-15|
    DE2453628A1|1975-05-22|
    SE7413980L|1975-05-13|
    JPS5321963B2|1978-07-06|
    NL7414662A|1975-05-14|
    IT1024810B|1978-07-20|
    FR2251139B1|1979-07-13|
    JPS5080019A|1975-06-28|
    US3967058A|1976-06-29|
    DE2453628C3|1980-10-23|
    FR2251139A1|1975-06-06|
    BE822021A|1975-03-03|
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    CH592984A5|1977-11-15|
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    引用文献:
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP12692373A|JPS5321963B2|1973-11-12|1973-11-12|
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